Modern communication systems often employ high peak to average ratio (PAR) signals. Linear amplification of high PAR signals was classically achieved by using high back off with a linear amplifier at the cost of very low power added efficiency (PAE).
Doherty amplifiers offer a potential solution by offering improved PAE under back off. Thus, Doherty amplifiers can reduce system cost, size, weight and power consumption primarily as a result of the substantially improved power added efficiency. A typical Doherty power amplifier has a main amplifier and a peaking amplifier with an input of the main amplifier coupled to an input of the peaking amplifier by a quarter-wave transmission line. An output from the main amplifier is coupled to an output from the peaking amplifier by a second quarter-wave transmission line. At low amplitude inputs, only the main amplifier is operational. At higher amplitude inputs, the peaking amplifier is also on; and the quarter-wave delay in the input to the peaking amplifier matches the quarter-wave delay in the output of the main amplifier to the output of the peaking amplifier with the result that the output of the peaking amplifier is in phase with the output of the main amplifier. For further information on Doherty amplifiers, please see Thomas H. Lee, Planar Microwave Engineering, pp. 667-69 (Cambridge University Press, 2004).
As shown in FIG. 1, the Doherty amplifier design may be extended to an N-way amplifier 100 having N legs or amplifiers where a main (or carrier) amplifier 110 is associated with the lowest power level, a first peaking amplifier 120-1 is associated with the next highest power level, and so on until a (N−1)th peaking amplifier 120-(N−1) is associated with the highest power level. Typically, the main amplifier is a Class AB or class B amplifier and the (N−1) peaking amplifiers are Class C amplifiers (or class AB amplifiers re-biased to emulate Class C amplifiers). Also shown in FIG. 1 are an input 130, an output 140, a load 150, an N-way signal splitter 160, a plurality of input delay lines 170-1 to 170-(N−1), and a plurality of output quarter-wave (λ/4) delay lines 180-1 to 180-(N−1). The input delay lines 170-1 to 170-(N−1) introduce increasing multiples of a quarter-wave (λ/4) length delay in the signal supplied from signal splitter 160 to the peaking amplifiers beginning with a quarter-wave delay in the signal supplied to peaking amplifier 120-1, a half-wave delay in the signal supplied to peaking amplifier 120-2 and so on to a delay of (N−1)λ/4 in the signal supplied to peaking amplifier 120-(N−1). The signal delays produced by the input delay lines are matched by the signal delays produced by the output delay lines.
Unfortunately, Doherty power amplifiers are considerably non-linear and thus usually require substantial digital pre-distortion (DPD) or analog pre-distortion (APD) to correct the non-linearity. The DPD (or APD) function is typically provided by a separate DPD (or APD) circuit block (not shown) that is located upstream of input 130. The DPD (or APD) function requires additional cost and power consumption.